1. Field of the Invention
The present invention provides a semiconductor package structure, a method for manufacturing the same. In particular, the present invention provides a semiconductor package structure comprising chips which are vertically stacked and electrically interconnected by through silicon plugs to a substrate unit using ultrasonic bonding methods. Additionally, test pads can be provided on the substrate unit or the chip to facilitate in process control. Also a method is disclosed that utilizes existing infrastructure thereby reducing cost.
2. Descriptions of the Related Art
The trend in advanced semiconductor packaging has been to reduce the form factor while improving electrical performance. This enables products for industry and consumers that are faster, cheaper and smaller. A common example is stacking of memory chips in a semiconductor package by using conventional materials and processes to assemble and test the resulting multi-chip package. Typically the electrical connections between the various stacked chips and the substrate [unit] are made by wire bonding. Stacking different types of chips is also possible but at the cost of greater electrical, thermal and mechanical complexity as well as the difficulties to achieve high yields with increased system level complexity within the package.
Through silicon vias (TSVs), or more accurately, through silicon plugs (TSPs) are a popular alternative approach to achieve higher levels of integration and form factor reduction for advanced semiconductor packaging. As the name implies, the electrical connection of the back and front of a semiconductor device enables the possibility of vertically assembling multiple chips in a package where previously only one chip was present. Accordingly, more semiconductor devices can be integrated into a smaller form factor. In addition, different types of semiconductor chips can be also integrated in a single package to create a so-called system in a package (SIP). Irrespective of the approach, the footprint of multiple packages in the printed circuit board is reduced which also reduces final product cost. Finally, interconnecting the chips by using TSPs can decrease the number of electrical connections necessary to the substrate [unit] since one substrate connection can service multiple chips. This also helps to simplify the assembly process and improve yield.
TSPs are also compatible with the more stringent signaling requirements necessary to achieve high performance. TSPs can be designed in with materials, shapes and sizes to provide high conductivity low inductance connections between the stacked chip and within the package and thereby facilitate efficient power delivery and improved signal quality. Additionally, the use of TSP structures decreases the need for complicated wire bonding of stacked chip because each chip need not be electrically connected to the substrate [unit] independently as is currently the case for memory devices in mass production of stacked packages. Also, since wire bonding has inductive properties that degrade the quality of electrical signals, especially at high frequencies; their removal improves the signal quality at a given frequency. Alternatively, higher signaling frequencies may be possible with the improved signal quality resulting from eliminating of parasitic inductance in a semiconductor device and package that is indeed smaller and faster.
Typically, high performance and small form factor packages are costly to manufacture. This is particularly the case when considering the use of TSPs to create three dimensional semiconductor devices within one package. For instance there are disparate competing approaches to implement stacked chips that use TSPs. For instance, there is so-called chip on chip (CoC) approaches where tested and singulated chips are arranged in a stacked configuration. Alternatively, there are wafer to wafer (WoW) schemes that contemplate stacking the chip in wafer form before singulation and with the anticipated yield loss when a good chip and bad chip on the corresponding wafers are vertically stacked together. Yet another approach is to stack a singulated Chip-on-Wafer (CoW), in a location where a good chip has been previously identified.
Implementation of each approach requires changes to the manufacturing process. As a preliminary matter, the process and location of making the TSV is unclear ranging from plasma etching to laser drilling. Some processes may be more suitable for implementation in the front-end semiconductor FAB that fabricates the integrated circuit while other approaches may be better suited for implementation in the back-end package and assembly factory. Additionally, there is no general approach to the TSP bonding method. For instance the electrical connections between stacked chips can be made by a variety of technologies such direct oxidizing fusion bonding, Cu—Cu bonding, Au—Au bonding, Au—Sn bonding, adhesion bonding or surface activation bonding. New process and materials increase the complexity and yield loss in the implementation of stacked chip using TSP with resulting increases in cost.
Irrespective of the process and integration choices that are made, there is considerable risk and uncertainty in implementation. As a result of increased complexity and possible yield loss, stacked packages using TSPs will be more expensive to fabricate. Consequently, TSP development has tended to focus on high performance systems that can command price premiums to offset the cost and complexity of the processes needed to construct stacked package using TSPs. Consequently, it is necessary to minimize the cost with the corresponding risk associated with its applications to adapt and to facilitate TSPs to the existing infrastructure and processes and to cost sensitive markets with wider implementations.